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diff --git a/academic/verilog/README b/academic/verilog/README new file mode 100644 index 0000000000..c8ebda2ee7 --- /dev/null +++ b/academic/verilog/README @@ -0,0 +1,5 @@ +Icarus Verilog is a Verilog simulation and synthesis tool. It operates as +a compiler, compiling source code written in Verilog (IEEE-1364) into some +target format. For batch simulation, the compiler can generate an intermediate +form called vvp assembly. This intermediate form is executed by the 'vvp' +command. For synthesis, the compiler generates netlists in the desired format. |