| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | academic/verilator: Added (Verilog HDL Simulator). |   Charles Daniels | 2020-03-20 | 4 | -0/+140 |
 |
index : slackbuilds | |
| Official Git Repository | slackbuilds-users@slackbuilds.org |
| summaryrefslogtreecommitdiffstats |