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# HOW TO EDIT THIS FILE:
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     |-----handy-ruler------------------------------------------------------|
yosys: yosys (A framework for Verilog RTL synthesis)
yosys:
yosys:
yosys:
yosys:   Yosys is a framework for Verilog RTL synthesis. It currently has
yosys: extensive Verilog-2005 support and provides a basic set of synthesis
yosys: algorithms for various application domains.
yosys:
yosys:
yosys:
yosys: